As AI workloads and high-performance computing (HPC) continue to demand faster data transfer and reduced latency, Microchip Technology has introduced its latest Switchtec Gen 6 PCIe switches. These are the industry’s first PCIe Gen 6 switches built on an advanced 3 nm process, offering lower power consumption and support for up to 160 lanes—enabling high-density connectivity in AI systems. They also incorporate advanced security features, including a hardware root of trust, secure boot, and post-quantum safe cryptography that complies with the Commercial National Security Algorithm Suite (CNSA) 2.0 standards.
Previous PCIe generations often created bandwidth bottlenecks during data transfers between CPUs, GPUs, memory, and storage—leading to underutilized hardware and wasted compute cycles. PCIe 6.0 doubles the bandwidth of PCIe 5.0 to 64 GT/s (giga transfers per second) per lane, providing the data throughput necessary to consistently supply powerful AI accelerators. Switchtec Gen 6 switches enable high-speed, low-latency connectivity between CPUs, GPUs, SoCs, AI accelerators, and storage devices, helping data center architects scale for the demands of next-generation AI and cloud infrastructure.
“Rapid innovation in the AI era is prompting data center architectures to move away from traditional designs and shift to a model where components are organized as a pool of shared resources,” said Brian McCarson, Corporate Vice President of Microchip’s Data Center Solutions Business Unit. “By expanding our proven Switchtec product line to PCIe 6.0, we’re enabling this transformation with technology that facilitates direct communication between critical compute resources and delivers the most powerful and energy-efficient switch we’ve ever produced.”
By serving as high-performance interconnects, these switches simplify and streamline the communication pathways between GPUs within a server rack—critical for minimizing signal loss and maintaining the low latency required by modern AI fabrics. The PCIe 6.0 standard also introduces FLIT (Flow Control Unit) mode, lightweight Forward Error Correction (FEC), and dynamic resource allocation. These enhancements improve efficiency and reliability in data transfers, particularly for the small data packets typical in AI workloads, resulting in higher throughput and reduced effective latency.
Switchtec Gen 6 PCIe switches feature 20 ports and 10 stacks, with each port supporting hot-plug and surprise-plug capabilities. The switches also support Non-Transparent Bridging (NTB) to connect and isolate multiple host domains, as well as multicast for one-to-many data distribution within a single domain. Designed with robust error containment, extensive diagnostics, and debug capabilities, they offer a wide range of I/O interfaces and include an integrated MIPS processor. Bifurcation options are available at x8 and x16, and input/output reference clocks are organized by PCIe stacks with four input clocks per stack.
Development Tools
The Switchtec Gen 6 PCIe switch family is supported by Microchip’s ChipLink diagnostic tools, which offer a comprehensive suite for debugging, diagnostics, configuration, and analysis via an intuitive graphical user interface (GUI). ChipLink connects using in-band PCIe or sideband signals such as UART, TWI, and EJTAG, allowing flexible and efficient monitoring throughout the design and deployment phases. Additionally, the switches are supported by the PM61160-KIT Switchtec Gen 6 PCIe Switch Evaluation Kit, which includes multiple interface options for prototyping and development.
